1. Field of the Invention
The present invention relates to a logic cell and a logic circuit of a pipeline structure configured by using the logic cells, more particularly relates to a technique for raising the speed of a logic operation and lowering power consumption.
2. Description of the Related Art
A xe2x80x9cdata path pipelinexe2x80x9d is the portion comprising the processors and pipeline registers in a processing block of a microprocessor. In order to realize operations at a high operating frequency, the general practice has been to divide the processors in the time direction and insert pipeline registers between the divided processors. One operation is executed over several cycles, but a new operation can be started at every cycle, so also operation results can be obtained at every cycle. Accordingly, if improving the operating frequency two-fold, the amount of operations possible in a certain time also doubles. In this way, the data path pipeline structure is a widely used technique for improvement of the operating speed and increase of the amount of operations.
FIGS. 1A to 1C show the configuration of a general data path pipeline. Here, as illustrated, the explanation will be made by taking as an example an operation for finding a cumulative sum of differential absolute values of data a1 to a4 and b1 to b4.
FIG. 1A shows the case where the operation is realized by a one-stage configuration processor. Here, it is assumed that the processor executes a required operation in a time Top. When the operation is actually carried out, there are a time Tcq until each pipeline register outputs valid data synchronous to a clock signal (generally also referred to as a xe2x80x9cvalid delayxe2x80x9d) and a time Tst required for a pipeline register to fetch data (generally also referred to as a xe2x80x9csetup timexe2x80x9d). The operation period T1 therefore becomes (T1=Top+Tcq+Tst)
As shown in FIG. 1B, when assuming that the operation process could be divided into exactly half in the time direction, the delay time of one processor becomes Top/2 at most. However, Tcq and Tst of the pipeline registers inserted are constant so far as the same registers are used, so the operation period T2 becomes (T2=Top/2+Tcq+Tst).
Similarly, as shown in FIG. 1C, where a four-stage configuration is employed, the operation period T4 becomes (T4=Top/4+Tcq+Tst).
Summarizing the problems to be solved by the invention, the conventional logic circuit of a pipeline structure is always constrained by a delay (Tcq+Tst) possessed by the registers. For this reason, even if the number of stages of the pipeline is increased, a commensurate improvement of the operating frequency cannot be obtained. Further, in this example, it was assumed that, when dividing the processors, the process became exactly halved, but sometimes such a skillful division is not possible and a side having a required operation time longer than Top/2 appears. In this case, there is a disadvantage that the operation period is further increased.
Further, since pipeline registers are inserted with respect to all data at the opening portions formed by the division, there are the problems that the size of the circuit is increased, the hardware overhead is large, and an increase of the power consumption is unavoidable.
An object of the present invention is to provide a logic cell capable of realizing a high speed logic operation with little hardware overhead and without using a pipeline register and capable of realizing a lowering of the power consumption and a logic circuit using the same.
To attain the above object, according to a first aspect of the present invention, there is provided a logic cell for performing a predetermined logic operation in accordance with a plurality of input signals, comprising a logic tree circuit having a plurality of switching elements connected between an output node and a reference potential, the switching element arranged nearest to the reference potential being controlled by a signal arriving earliest among the plurality of input signals, and the switching element arranged nearest to the out put node being controlled by a signal arriving latest among the plurality of input signals, and an output circuit connected to the output node and outputting the signal of the output node in accordance with the signal arriving latest among the plurality of input signals.
According to a second aspect of the present invention, there is provided a logic circuit comprising an input register for holding a plurality of input signals; a logic operation circuit comprising a plurality of logic cells each receiving a signal held by the input register, performing a predetermined logic operation, and outputting operation results to the next logic cell; an output register for holding and outputting the output signal of a last logic cell; and a reset circuit for resetting the input register when the output signal of a monitor use logic cell selected from among the plurality of logic cells is in a predetermined state in accordance with the output of the monitor use logic cell; the logic cell comprising a logic tree circuit having a plurality of switching elements connected between an output node and a reference potential, the switching element arranged nearest to the reference potential being controlled by a signal arriving earliest among the plurality of input signals, and the switching element arranged nearest to the output node being controlled by a signal arriving latest among the plurality of input signals, and an output circuit connected to the output node and outputting the signal of the output node in accordance with the signal arriving latest among the plurality of input signals.
Preferably the logic tree circuit is formed by Shannon expansion of the plurality of input signals in order from the latest arrival.
Preferably the output circuit has a latch circuit for holding the signal level of the output node.
Preferably the input register converts each input signal to a pair of signals, and each signal pair takes at least three logic states of a logic 0 (0, 1), a logic 1 (1, 0), and a blank (0, 0).
More preferably, when the input signal arriving the latest takes the blank state, the output circuit of each logic cell other than the last logic cell outputs a signal indicating the blank state, and the output circuit of the last logic cell holds and outputs the operation result immediately before that.
More preferably, when the output of the monitor use logic cell takes a state other than the blank state, the reset circuit resets the input register.
Preferably, when the input register is reset, all output signals are held at signals indicating the blank state.
That is, according to the present invention, there is provided a logic circuit for performing a predetermined logic operation in accordance with a plurality of input signals comprising a logic operation circuit configured by a plurality of logic cells connected in series. Each input signal is converted to a two-wire signal, that is, 2 bits of data, and logic codes representing at least three logic states of the logic 0, logic 1, and the blank state are comprised by these two-wire signals. Each logic cell is configured by a logic tree circuit formed by Shannon expansion of the input signals in order of the latest arrival and an output circuit.
In the logic operation circuit comprising the plurality of logic cells, a predetermined logic cell existing in the middle is selected as the monitor use logic cell. When the output of the related monitor use logic cell becomes a code other than the blank code ((0, 1) or (1, 0), below, this will be referred to as a valid logic code), all outputs of the input register are switched to the blank code by the reset circuit. This blank code is propagated to the output side by the logic cells. When the output of the monitor use logic cell becomes the blank code, the reset of the input register is released, whereby the input signal is converted to a two-wire code synchronous to the clock signal and input to each logic cell. Predetermined logic operations are carried out in accordance with these input codes. When the output of the monitor use logic cell becomes a valid logic code, the input register is reset, and a blank code is input to each logic cell again and propagated to the output side.
In the logic circuit configured in this way, a pipeline operation can be realized without providing pipeline registers between the plurality of logic cells, an increase of the circuit scale can be suppressed, the hardware overhead can be avoided, and a raising of speed of the operation, and a reduction of the power consumption can be realized.